Increasing the common mode range of a circuit

ABSTRACT

Increasing the input common-mode range of a circuit which accepts differential signals as inputs. Such an increase may be attained by correcting an input signal at continuous levels or at 2 or more discrete levels) without changing the strength represented by the input signal. In an embodiment, the common-mode component of an input signal is measured, and a correction voltage proportional to the difference between the measured common-mode component and a reference voltage, is generated. The correction voltage is coupled to the input terminals of the differential circuit to correct for any deviations from a desired level of common-mode voltage at the input terminals of the differential circuit. The approaches are applied to a switched-capacitor differential amplifier used in a sample-and-hold portion of an ADC.

BACKGROUND

1. Field of the Invention

The present invention relates generally to the design of electroniccircuits, and more specifically to a method and apparatus to increasethe range of common mode voltages a circuit can operate with, whileprocessing input signals.

2. Related Art

An electronic circuit generally accepts one or more input signals,processes them in some manner and correspondingly provides one or moreoutput signals. For example, an amplifier may accept an audio signal andprovide an amplified version of the audio signal as an output.

All signals in a circuit are referenced to one or more referenceterminals, usually a ground terminal. For example, an input signal maybe applied between an input terminal and a terminal connected to aground reference point(circuit ground). The corresponding output signalmay be provided between an output terminal and the circuit ground. Aninput (or output) signal which is referenced to a common ground terminalof a circuit(circuit ground) is called a single-ended signal.

In some environments, it is desirable to provide input signals to acircuit on terminals none of which are connected directly to circuitground. This may be done in environments where the input signals areweak (low signal strength) and the entire circuit is operating in thepresence of considerable noise (unwanted interfering signals).

For example, in a data-acquisition and control system, input signals maycome from transducers located some distance from the main processingcircuitry. Signals from transducers are typically low strength (weak)signals and may have to travel appreciable distances (through wires)before they can be processed.

In such environments, an input signal to a circuit is applied betweentwo terminals (called differential input terminals), and the inputsignal is called a differential input signal and is not referenced tocircuit ground. For example, a differential amplifier such as anoperation amplifier (OPAMP) has two input terminals, inverting andnon-inverting, between which a differential input signal may be applied.The OPAMP may amplify such a differential input signal and provide anoutput signal which may be single-ended or differential.

A differential signal (as in above environments) is characterized by astrength which equals the difference between the voltage(or current)values present on the two input terminals. The input signal may alsocontain a signal component which is common to both the input terminals.Such a common component is referred to as a common mode signal and isdefined as the average of the voltage (or current) values present on thetwo input terminals.

A circuit such as an operational amplifier noted above may also receivesingle-ended input signals. In such a case, one input terminal of thecircuit is connected to the single-ended signal and a second terminal ofthe circuit is connected to a reference voltage. Such a circuit is alsocharacterized by a common-mode voltage (strength) at the two inputterminals.

There has been a general constraint that the common-mode signal input(or equivalently the common-mode voltage/strength at the inputterminals) to circuits (such as operational amplifiers) be limited to acertain range in order to ensure proper circuit functioning. Forexample, in the case of operational amplifiers there is a maximumspecified common-mode voltage range for an input signal.

It is also desirable that the input common-mode range of a circuit (suchas a differential amplifier) with differential (or single-ended) inputsbe as high as possible, thus allowing a wide range of input signals tobe processed. This is further described below with respect to anenvironment containing a sample-and-hold stage in an analog-to-digitalconverter (ADC).

FIG. 1 is a block diagram of a pipeline ADC in one embodimentillustrating the need to increase the input common mode range of aninput (sample-and-hold circuitry) circuit. ADC 100 is shown containingsample and hold amplifier (SHA) 110, stages 120-1 through 120-S, digitalerror correction block 130 and reference buffer 150. Each block isdescribed below in further detail.

Reference buffer 150 generates a reference voltage (Vref) on path 152typically from a constant DC voltage (Vdc, e.g., bandgap referencevoltage, well known in the relevant arts). Reference voltage (Vref) isused in various stages of the ADC for comparison against the signals atthe respective inputs (on paths 111-1 through 111-S).

Digital error correction block 130 receives sub-codes from variousstages (on paths 123-1 through 123-S respectively), and generates adigital code corresponding to the sample received on path 101. Variouserror correction approaches, well known in the relevant arts, may beused to correct any errors in the received sub-codes. The generateddigital code is provided on path 139 as a final digital codecorresponding to the voltage of a sample on the input analog signal at aparticular time instant.

Each stage 120-1 through 120-S generates a sub-code (based on thereference signal Vref received on path 152) corresponding to a voltagelevel of an analog signal received as an input, and an amplified residuesignal as an input to a (any) next stage. For example, stage 120-1converts a voltage level on path 111-1 to generate a sub-code on path123-1, and the amplified residue signal generated on path 111-2 isprovided as an input to stage 120-2.

A common reference signal Vref is provided to stages 120-1 through120-S. Each of stages 120-1 through 120-S may further containvarious(logical) components such as a flash ADC, digital-to-analogconverter (DAC), subtractor and gain amplifier as is well known in therelevant arts.

SHA 110 samples the input analog signal received on path 101 and holdsthe voltage level of the sample on path 111-1 for further processing.Path 101 contains two terminals between which an input differentialsignal may be applied. As noted above, the differential signals containa common mode signal. The need for a high range of common mode signalcan be better appreciated by examining the details and operation of SHA110 in one embodiment.

Various terms used in the description and subsequent analysis are firstlisted below:

INP is the voltage at terminal 290-1

INM is the voltage at terminal 290-2

OUTP is the voltage at terminal 270-1

OUTM is the voltage at terminal 270-2

INP−INM represents the strength of the differential input signalreceived across terminals 290-1 and 290-2 and is the signal of interest.

OUTP−OUTM represents the strength of differential output signal providedacross terminals 270-1 and 270-2 and is the signal of interest

INPCM=(INP+INM)/2), wherein INPCM is the common-mode voltage present ininput signal applied across terminals 290-1 and 290-2

OUTCM is the common-mode voltage present at output terminals 270-1 and270-2 due to application of an internally generated (in differentialamplifier 260) reference voltage (REFCM). (In the interest of clarity,it is assumed for the purpose of this description that the output commonmode feedback loop (noted earlier) is perfect, and that OUTCM gets setexactly to REFCM. For this reason, OUTCM and REFCM may be usedinterchangeably to refer to the same voltage.

REFCM(equal to (REFP+REFM)/2) is a common-mode voltage generated byinternal (to differential amplifier 260) reference voltages REFP andREFM.

INCM is the common-mode voltage applied at input terminals (280-1 and280-2) of differential amplifier 260 due to application of a referencevoltage INCM and represents the value of the common-mode voltage thatmust be maintained at input terminals 280-1 and 280-2.

AMPINP is the voltage at 280-1 in the hold phase and AMPINM is thevoltage at 280-2 in the hold phase. AMPCM is the effective common-modevoltage present at terminals 280-1 and 280-2 due to all sources ofcommon-mode voltage (namely, INPCM, OUTCM and INCM) during the holdphase (between durations 391-392 of FIG. 3). AMPCM is equal to(AMPINP+AMPINM)/2.

Gd is the overall gain of the SHA 110 and is equal to(OUTP−OUTM)/(INP−INM).

Ao is the open loop differential gain of the differential amplifier 260which is equal to (voltage at terminal 270-2−voltage at terminal270-1)/(AMPINP−AMPINM)

FIG. 2 shows the internal details of SHA 110 in one embodiment. SHA 110receives a differential input signal (that needs to be sampled at heldfor analog-to-digital conversion and further processing) acrossterminals 290-1 and 290-2 (logically contained in path 101), and isshown containing elements differential amplifier 260, switches 250-1,250-2, 220-1, 220-2, 240-1 and 240-2, and capacitors 21 230-2. Eachelement is described below in further detail.

Differential amplifier 260 amplifies the difference of the voltagespresent across terminals 280-1 and 280-2, and provides an amplifiedoutput voltage across terminals 270-1 and 270-2. The differential outputis connected (fed-back) to the terminals 280-1 and 280-2 throughcapacitors 210-1 and 210-2. Due to the feedback connection, differentialamplifier 260 provides a differential output signal (across terminals270-1 and 270-2), which is equal to the differential input signal. Thedifferential output signal is used in subsequent stages (illustrated inFIG. 1) for further processing.

To ensure proper operation of differential amplifier 260, terminals280-1 and 280-2 generally need to be maintained at a constantpre-determined bias potential. To achieve this, reference voltages areapplied to terminals 280-1 and 280-2 through switches 220-1 and 220-2.Such an application causes a desired common-mode voltage to bemaintained at terminals 280-1 and 280-2. The reference voltages notedabove are selected such that the virtual ground nodes of the amplifier(280-1 and 280-2) are at an optimum value to ensure reliable operation.That is, the transistors contained in differential amplifier 260 arebiased such that the amplifier operates with the desired high DC gain.

Similarly, the output terminals 270-1 and 270-2 of differentialamplifier 260 may also need to be maintained at a constantpre-determined bias potential to ensure proper operation of anydifferential circuitry whose inputs may be connected to output terminals270-1 and 270-2 of differential amplifier 260. This is achieved by acommon mode feedback loop (not shown) which forces the output commonmode which is equal to ((voltage at terminal 270-1+voltage at terminal270-2)/2) to an internally generated voltage REFCM(equal to(REFP+REFM)/2).

Capacitors 230-1 and 230-2 represent parasitic capacitances at terminals280-1 and 280-2 respectively. Switches 250-1, 250-2, 240-1 and 240-2,and capacitors 210-1, 210-2 operate to sample an input signal appliedacross input terminals 290-1 and 290-2 and hold the sampled value foramplification by differential amplifier 260. The manner in which thissample-and-hold operates is described below with reference to FIG. 3,which contains a timing diagram used to illustrate the sample and holdphases of SHA 110.

SHA 110 operates using two phases, shown in FIG. 3 as sampling phase 370and hold phase 390. In the first phase (sampling phase 370) switches250-1, 250-2, 220-1 and 220-2 are closed at time points 371 and theremaining switches 240-1 and 240-2 are kept open. As a result,capacitors 210-1 and 210-2 are ideally charged (in duration between371-372) to the voltage of input signal present across terminals 290-1and 290-2 by time point 372, and, 230-1 and 230-2 are ideally charged(in duration between 371-372) to the voltage (INCM) present at terminals225-1 and 225-2.

In the second phase (between durations 391-392), feedback switches 240-1and 240-2 are closed and switches 250-1, 250-2, 220-1 and 220-2 are keptopen. This causes the output (across terminals 270-1 and 270-2) ofamplifier 260 to take on a magnitude that is a function of the inputsignal (received on terminals 290-1 and 290-2), and the referencevoltages INCM (applied on terminals 225-1 and 225-2) and OUTCM (appliedon terminals 225-1 and 225-2). Expressions for the magnitude of theoutput voltage and the magnitudes of the differential and common-modevoltages at various nodes of SHA 110 are derived below.

As differential amplifier 260 is connected as a unity gain amplifier,the differential output voltage (OUTP−OUTM) is equal in magnitude to thedifferential input voltage (INP−INM), which is as required.

The common-mode voltages at various nodes are derived below. For thesake of clarity, voltages at various nodes are derived assuming onlycommon-mode voltages are present.

During the sample phase switches 250-1, 250-2, 220-1 and 220-2 areclosed, while switches 240-1 and 240-2 are open.

Therefore charge at each of input terminals 280-1 and 280-2 at the endof the sample phase is given by:Q=C _(s)(INCM−INPCM)+C _(p)(INCM)   Equation (1)

During the hold phase, switches 240-1 and 240-2 are closed and switches250-1, 250-2, 220-1 and 220-2 are open.

Therefore charge at each of input terminals 280-1 and 280-2 at the endof the hold phase is given by:Q=C _(s)(AMPCM−OUTCM)+C _(p)(AMPCM)   Equation (2)

Input terminals 280-1 and 280-2 are high impedance nodes and hencecharge at these nodes must be conserved. Therefore, equating equations 1and 2 gives $\begin{matrix}{{AMPCM} = {{INCM} + {\left( \frac{{OUTCM} - {INPCM}}{C_{s} + C_{p}} \right)C_{s}}}} & {{Equation}\quad(3)}\end{matrix}$

Thus, it may be seen that due to the feedback of the output signal andapplication of an input signal, AMPCM has a value different from therequired value of INCM, the difference being equal to(OUTCM−INPCM)C_(s)/(C_(s)+C_(p)).

As may be seen from the above description, large variations in INPCM,cause correspondingly large variations in AMPCM, thereby affecting thenormal operation of differential amplifier 260 and limiting its use tocases where the common-mode voltages in the input signal fall within anarrow range of values.

However, input signals can be received with a wide range of common modevoltages on path 101, for example, because the input signal may havebeen generated in an earlier circuit which is referenced to a differentground potential (in comparison with SHA 110). Alternatively, commonnoise component might have been added as common mode voltage on bothterminals 290-1 and 290-2.

Various aspects of the present invention operate to increase the inputcommon-mode range of a circuit (e.g., SHA 110) which acceptsdifferential signals as inputs.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be described with reference to the followingaccompanying drawings, which are described briefly below.

FIG. 1 is a block diagram illustrating an example environment in whichvarious aspects of the present invention can be implemented.

FIG. 2 is a schematic diagram of a prior sample-and-hold amplifier.

FIG. 3 is a timing diagram illustrating the sample and hold phases of asample-and-hold amplifier.

FIG. 4A is a schematic diagram illustrating the manner in which acorrection voltage in a single ended form may be generated to correctfor a common-mode voltage in an input signal in one embodiment.

FIG. 4B is a schematic diagram illustrating the manner in which acorrection voltage in a differential form may be generated to correctfor a common-mode voltage in an input signal in one embodiment.

FIG. 5 is a schematic diagram illustrating a correction circuitry whichmay be used to correct for a common-mode voltage in an input signal inone embodiment.

FIG. 6A is an equivalent circuit of a sample-and-hold amplifier during asample phase in one embodiment.

FIG. 6B is an equivalent circuit of a sample-and-hold amplifier during ahold phase in one embodiment.

FIG. 7 is a schematic diagram illustrating a correction circuitry in asecond embodiment which may be used to correct for a common-mode voltagein an input signal.

FIG. 8A is a schematic diagram illustrating a correction circuitry whichmay be used to correct for a common-mode voltage in an input signalreceived in differential form in a third embodiment.

FIG. 8B is a schematic diagram illustrating a correction circuitry whichmay be used to correct for a common-mode voltage in an input signalreceived in single ended form in a third embodiment.

FIG. 9 is a block diagram illustrating the manner in which a correctionvoltage may be generated by activating the appropriate switches shown inFIGS. 8A and 8B.

FIG. 10A is a graph illustrating the manner in which correction voltageis at continuous levels in an embodiment of the present invention.

FIG. 10B is a graph illustrating the manner in which correction voltageis at discrete levels in another embodiment of the present invention.

FIG. 11 is a block diagram of an example device in which various aspectsof the present invention can be implemented.

In the drawings, like reference numbers generally indicate identical,functionally similar, and/or structurally similar elements. The drawingin which an element first appears is indicated by the leftmost digit(s)in the corresponding reference number.

DETAILED DESCRIPTION

1. Overview

According to an aspect of the present invention, a correction voltagewhich corrects an input signal by a voltage level (one of more than 2levels) proportionate to the common mode voltage of the input signal isapplied to ensure that a corrected signal (generated from the inputsignal) has a constant common mode voltage. As a result, any circuitprocessing the corrected signal can be implemented independent of thelevel of the common mode voltage (within a range) of the input signal.Thus, the overall circuit can be implemented with an input signal havinga wide range of common mode voltages.

In an embodiment (described below in further detail), such a feature isobtained by measuring the voltage level of the common mode present on aninput differential signal, and generating a difference voltage betweensuch a common-mode voltage and a reference voltage. This differencevoltage is amplified by a suitable factor to generate a correctionvoltage, which is subtracted from the common-mode voltage present in theinput signal so as to maintain the common-mode voltage presented to theinput terminals of a circuit at a constant pre-determined level.

Thus, as long as the common-mode voltage on the input signal is within acertain limit, the common-mode voltage of the output/corrected signalpresented for further processing is maintained constant. This allows theoverall solution to be used with input signals that may contain a widerrange of common-mode voltages without affecting the operation of thecircuit.

In an embodiment that contains a sample-and-hold amplifier usingswitched-capacitor techniques, input common-mode voltage at thedifferential inputs is maintained constant by: (1) applying a correctionvoltage through a capacitor of a suitable value to one input terminal ofthe amplifier during the hold phase; (2) applying the same correctionvoltage through a capacitor of

the same value to the second input terminal of the amplifier during thehold phase of operation; and (3) applying a reference voltage to each ofthe two input terminals through the same set of capacitors during thesample phase of operation.

In another embodiment of the above- noted sample-and-hold amplifier,input common-mode voltage at the differential inputs is maintainedconstant by: (1) applying a correction voltage through a capacitor of asuitable value to one input terminal of the amplifier during the holdphase; (2) applying the same correction voltage through a capacitor ofthe same value to the second input terminal of the amplifier during thehold phase of operation; and (3) applying an opposite correction voltageto each of the two input terminals through the same set of capacitorsduring the sample phase of operation.

Several aspects of the invention are described below with reference toexamples for illustration. It should be understood that numerousspecific details, relationships, and methods are set forth to provide afull understanding of the invention. One skilled in the relevant art,however, will readily recognize that the invention can be practicedwithout one or more of the specific details, or with other methods, etc.In other instances, well-known structures or operations are not shown indetail to avoid obscuring the features of the invention.

2. Generating Correction Voltages

With respect to equation 2, it may be appreciated that if the term(OUTCM−INPCM)C_(s)/(C_(s)+C_(p)) is cancelled or its magnitude reducedby a suitable approach, then the input signal may be allowed to containa wider range of common-mode voltages (represented by INPCM) withoutaffecting the operation of a differential circuit such as SHA 110.

This is achieved according to an aspect of the present invention bygenerating a correction voltage and canceling the undesirable componentof common-mode voltage (OUTCM−INPCM)C_(s)/(C_(s)+C_(p)), as is describedfurther below with reference to FIGS. 4A and 5.

FIG. 4A contains a circuit (correction signal generator) that may beused to generate the correction voltage noted above and may beimplemented internally in SHA 110. Merely for illustration, the circuitis described in the context of FIGS. 1-2 described above. However, thefeatures can be implemented in various other environments, as will beapparent to one skilled in the relevant arts by reading the descriptionprovided herein. The circuit is shown containing differential amplifier420, resistors 410-1 and 410-2 and capacitor 440. Each element isdescribed below in further detail.

Resistors 410-1 and 410-2 have the same value and are used to form avoltage divider network to generate a voltage on path 412-1 which is theaverage (and therefore equal to the common mode voltage) of the voltagespresent on terminals 290-1 and 290-2.

Capacitor 440 is connected between path 412-1 and ground, and incombination with resistors 410-1 and 410-2 acts as a low pass filter.Such a combination, therefore, measures an “average” value of the inputcommon mode(on terminals 290-1 and 290-2) and makes such a valueavailable on path 412-1. The time period of this average is proportionalto the filter time constant as set by the product of the values ofresistors 410-1/410-2 and capacitor 440.

Differential amplifier 420 is used to amplify the difference between theinputs at terminals 412-1 and 412-2 by a required gain. The circuitryused to set the required gain is not shown, as being well understood toone skilled in the relevant arts.

When an input signal containing a common voltage INPCM is applied acrossterminals 290-1 and 290-2, the resistive divider network formed byresistors 410-1 and 410-2 generates a voltage equal to INPCM on path412-1. A voltage equal to the output common-mode voltage OUTCM (which isforced to REFCM by an internally generated voltage because of the commonmode feedback loop mentioned earlier) of differential amplifier 260 isapplied at terminal 412-2.

Differential amplifier 420 amplifies the difference of OUTCM and INCM bya required factor to generate a correction voltage, that is, the outputof amplifier 420 has a value (OUTCM−INPCM)*G, wherein G is the gain ofdifferential amplifier 420.

Referring to equation 3, it may be seen that if the gain G in amplifier420 is set to C_(s)/(C_(s)+C_(p)), then the output of differentialamplifier 420 will be equal to (OUTCM−INPCM)C_(s)/(C_(s)+C_(p)), whichis the undesirable component of the common-mode voltage present at theinput terminals 280-1 and 280-2 of differential amplifier 260 of FIG. 2.If this output of differential amplifier 420 is subtracted from theeffective value of common-mode voltage AMPCM, then the common-modevoltage at input terminals 280-1 and 280-2 may be maintained at thedesired value represented by INCM.

While the circuit of FIG. 4A generates the correction voltage in asingle-ended form, it should be appreciated that some circuits (e.g.,the circuit of FIG. 7, described below) may need the output indifferential form. An embodiment of such circuit generating thecorrection voltage in differential form is described below in furtherdetail.

FIG. 4B contains circuitry substantially similar to that of FIG. 4A anda detailed description is not provided here in the interest ofconciseness. The only difference from FIG. 4A is that output terminals430-1 and 430-2 of differential amplifier 420 provide correctionvoltages (INCORRP and INCORRM, referred to in the description below) indifferential form.

The manner in which the correction voltage generated using theapproach(es) described above is used to increase the input common moderange is described below with reference to FIG. 5.

3. Applying Correction Voltage to Increase Input Common-Mode Range

FIG. 5 contains a circuit used to apply a correction voltage to maintainthe common-mode voltage at the input terminals of a differentialamplifier at a constant value. For conciseness and clarity, some of thecomponents of FIG. 2 are shown retained in FIG. 5. Thus, sample and holdamplifier (SHA) 500 (which can be used in place of SHA 110) is showncontaining differential amplifier 260, switches 250-1, 250-2, 220-1,220-2, 240-1, 240-2, 540-1 and 540-2, and capacitors 210-1, 210-2,230-1, 230-2, 510-1 and 510-2.

Differential amplifier 260, switches 250-1, 250-2, 220-1, 220-2, 240-1and 240-2, and capacitors 210-1, 210-2, 230-1 and 230-2 operate similarto in FIG. 2, and the corresponding description is not repeated in theinterest of conciseness.

In the descriptions to follow input signal refers to a signal appliedacross terminals 290-1 and 290-2, and a corrected signal (in terms ofits common mode voltage) refers to a signal across terminals 280-1 and280-2, whose common-mode strength has been corrected to a desired level.

Switches 540-1 and 540-2 and capacitors 510-1 and 510-2 comprise acorrection circuitry, which operate to increase the input common-moderange of SHA 500 as described below.

During the sample phase of operation of SHA 500, switches 540-1 and540-2 are connected to terminals 520-1 and 520-2 respectively. Duringthe hold phase of operation of SHA 500, switches 540-1 and 540-2 areconnected to terminals 530-1 and 530-2 respectively.

Terminals 520-1 and 520-2 are connected to reference voltage REFCM (aninternally generated voltage). Terminals 530-1 and 530-2 are connectedto a correction voltage (VCORR) which may be generated internally in SHA500 in a suitable manner using the approaches described above withrespect to FIG. 4A. It is now shown below, how the application of acorrection voltage in the circuit of FIG. 5 maintains the common-modevoltage constant. For the sake of clarity, voltages at various nodes arederived assuming only common-mode voltages are present.

Charge at each of input terminals 280-1 and 280-2 at the end of thesample phase is given by:Q=C _(s)(INCM−INPCM)+C _(p)(INCM)+C _(x)(INCM−OUTCM)   Equation (4)

Charge at each of input terminals 280-1 and 280-2 at the end of the holdphase is given by:Q=C _(s)(AMPCM−OUTCM)+C _(p)(AMPCM)+C _(x)(AMPCM−VCORR)   Equation (5)

The charge at input terminals 280-1 and 280-2 must be conserved (asnoted earlier). Therefore equating equations 3 and 4 and re-arrangingthe terms gives: $\begin{matrix}\begin{matrix}{{AMPCM} = {{INCM} + \frac{\left( {{OUTCM} - {INPCM}} \right)*C_{S}}{C_{s} + C_{p} + C_{x}} -}} \\{{{OUTCM}*\frac{C_{x}}{C_{s} + C_{p} + C_{s}}} - \frac{{VCORR}*C_{x}}{C_{s} + C_{p} + C_{x}}}\end{matrix} & {{Equation}\quad(6)}\end{matrix}$

From equation 6, it may be seen that if (VCORR*Cx) is equal to(OUTCM*(Cs+Cx)−INPCM*Cs), then AMPCM will be maintained at a level equalto INCM, which is the desired level. Equation 7 below gives the requiredexpression:C _(x) *VCORR=((OUTCM−INPCM)*C _(s))−OUTCM*C _(x)   Equation (7)

The values of Cx and VCORR may be suitably chosen to achieve the aboverequirement.

Though it is possible to maintain AMPCM at the desired common-mode levelby choosing values of VCORR and Cx according to the equations describedabove, the disadvantages with having larger values of Cx is that itaffects the closed loop bandwidth, the distortion and the differentialgain (Gd) of differential amplifier 260, as is described below withreference to FIGS. 6A and 6B. An expression for closed loop bandwidthand Gd is derived below in order to show its dependence on the value ofCx. Voltages at input terminals 280- 1 and 280-2 are represented by V+and V− respectively.

FIGS. 6A and 6B show equivalent circuits of a portion of SHA 500 showinginputs and outputs of differential amplifier 260 during the sample phaseand hold phase respectively. Dotted line 610 represents the virtualshort between input terminals 280-1 and 280-2 of differential amplifier260.

From FIG. 6A:C _(s)(INCM−INP)+C _(p)INCM=C _(p) V ⁺ +C _(s)(V ⁺−OUTM)   Equation (8)

From FIG. 6B:C _(s)(INCM−INM)+C _(p)INCM=C _(p) V ⁻ +C _(s)(V ⁻−OUTP)   Equation (9)

Subtracting equation 9 from equation 8 gives:C _(s)(INM−INP)=C _(p)(V ⁺ −V ⁻)+C _(s)(V ⁺ −V ⁻)+C _(s)(OUTP−OUTM)  Equation (10)

Further:(V ⁺ −V ⁻)*(−A _(o))=OUTP−OUTM   Equation (11)

Rearranging the terms in equation 11 gives: $\begin{matrix}{\left( {V^{+} - V^{-}} \right) = \frac{{OUTP} - {OUTM}}{- A_{o}}} & {{Equation}\quad(12)}\end{matrix}$

wherein A₀ is the open-loop gain of differential amplifier 260.

Substituting the expression for (V⁺−V⁻) from equation 12 in equation 10gives: $\begin{matrix}{{C_{s}\left( {{INP} - {INM}} \right)} = {{C_{p}\left\lbrack \frac{{OUTP} - {OUTM}}{A_{0}} \right\rbrack} + {C_{s}\left\lbrack \frac{{OUTP} - {OUTM}}{A_{0}} \right\rbrack} + {C_{s}\left( {{OUTP} - {OUTM}} \right)}}} & {{Equation}\quad(13)}\end{matrix}$

Rearranging the terms of equation 13 gives: $\begin{matrix}{{C_{s}\left( {{INP} - {INM}} \right)} = {\left( {{OUTP} - {OUTM}} \right)\left\lbrack {\frac{C_{s}}{A_{o}} + \frac{C_{p}}{A_{o}} + C_{s}} \right\rbrack}} & {{Equation}\quad(14)}\end{matrix}$

Rearranging the terms of equation 14 gives: $\begin{matrix}{\left( {{OUTP} - {OUTM}} \right) = \frac{\left( {{INP} - {INM}} \right)}{\left\lbrack {1 + \frac{1}{A_{0}} + \frac{C_{p}}{C_{s}A_{0}}} \right\rbrack}} & {{Equation}\quad(15)}\end{matrix}$

When correction is applied using a correction voltage VCORR in themanner described earlier, the relation represented by equation 15becomes: $\begin{matrix}{\left( {{OUTP} - {OUTM}} \right) = \frac{\left( {{INP} - {INM}} \right)}{\left\lbrack {1 + \frac{1}{A_{0}} + \frac{C_{p}}{C_{s}A_{0}} + \frac{C_{x}}{C_{s}A_{0}}} \right\rbrack}} & {{Equation}\quad(16)}\end{matrix}$

From equation 16, it may be seen that overall transfer function of theSHA is given by: $\begin{matrix}{\frac{\left( {{OUTP} - {OUTM}} \right)}{\left( {{INP} - {INM}} \right)} = \frac{1}{\left\lbrack {1 + \frac{1}{A_{0}} + \frac{C_{p}}{C_{s}A_{0}} + \frac{C_{x}}{C_{s}A_{0}}} \right\rbrack}} & {{Equation}\quad(17)}\end{matrix}$

If the open-loop gain Ao of differential amplifier 260 were infinite,then Gd would be equal to unity since terms containing A₀ would be equalto zero, and output differential voltage would be equal to inputdifferential voltage, as required.

However, as A₀ has a finite value, it may be seen from equation 18 thatGd would be less than one.

Therefore, it may be appreciated that to achieve a gain Gd which is asclose to unity as possible, Cp and Cx must have very small values. (Cpis chosen to have a value as small as possible).

Further, substituting Ao=Adc/(1+s/ω_(p)), wherein Adc is the open loopDC gain of the differential amplifier and ω_(p) is the pole of theamplifier) gives: $\begin{matrix}{\frac{{OUTP} - {OUTM}}{{INP} - {INM}} = {1/\left\lbrack {1 + {{\left( {C_{S} + C_{P} + C_{X}} \right)/C_{S}}*A_{dc}} + {s/\left( {A_{dc} \cdot \omega_{p} \cdot {\left( {C_{S} + C_{P} + C_{X}} \right)/C_{S}}} \right)}} \right\rbrack}} & {{Equation}\quad 17A}\end{matrix}$

wherein the closed loop bandwidth is equal to the[Adc·ω_(p)·Cs/(Cs+Cp+Cx)]

So as the value of Cx increases the closed loop bandwidth becomes lessand more power is needed. Also the factor Cs/(Cs+Cp +Cx) being smallcauses less distortion suppression by the amplifier.

It may be appreciated from the above description that a choice of alarge value of Cx to order to satisfy the requirement of equation 7 willaffect closed loop bandwidth, distortion and closed loop differentialgain Gd.

Therefore, an improved approach to maintaining a constant common-modevoltage at the input terminals of differential amplifier 260 may be usedand is described below with reference to FIG. 7.

4. Improved Approach to Applying Correction Voltage

FIG. 7 is a circuit diagram of a sample and hold amplifier (SHA)illustrating the manner in which correction voltage can be appliedwithout affecting differential gain of the SHA. Sample and holdamplifier SHA 700 (which can be used in place of SHA 110) is showncontaining differential amplifier 260, switches 250-1, 250-2, 220-1,220-2, 240-1, 240-2, 710-1 and 710-2, and capacitors 210-1, 210-2,230-1, 230-2, 740-1 and 740-2. Each component is described below infurther detail.

Differential amplifier 260, switches 250-1, 250-2, 220-1, 220-2, 240-1and 240-2, and capacitors 210-1, 210-2, 230-1 and 230-2 operate similarto as described above with respect to FIG. 2, and the description is notrepeated in the interest of conciseness.

Switches 710-1 and 710-2, and capacitors 740-1 and 740-2 comprise acorrection circuitry, which operate to increase the input common-moderange of SHA 700 as described below.

During the sample phase of operation of SHA 700, switches 710-1 and710-2 are connected to terminals 720-1 and 720-2 respectively. Duringthe hold phase of operation of SHA 700, switches 710-1 and 710-2 areconnected to terminals 730-1 and 730-2 respectively.

Terminals 720-1 and 720-2 are connected to a correction voltage INCORRP.Terminals 730-1 and 730-2 are connected to a correction voltage INCORRM.INCORRP and INCORRM may be generated internally in SHA 700 in a suitablemanner. One such approach is to generate INCORRP and INCORRM as adifferential voltage riding on a common mode voltage.

that is,INCORRP=VCOMMON+VCORRINCORRM=VCOMMON−VCORR   Equation 18A

wherein INCORRP and INCOOM may be generated as described above withreference to FIG. 4B.

It is now shown below, how the application of correction voltagesINCORRP and INCORRM in the circuit of FIG. 7 maintains the common-modevoltage constant. For the sake of clarity, voltages at various nodes arederived assuming only common-mode voltages are present.

Charge at each of input terminals 280-1 and 280-2 at the end of thesample phase is given by:Q=C _(s)(INCM−INPCM)+C _(p)INCM+C _(x)(INCM−INCORRP)   Equation (18)

Charge at each of input terminals 280-1 and 280-2 at the end of the holdphase is given by:Q=C _(s)(AMPCM−OUTCM)+C _(p) AMPCM+C _(x)(AMPCM−INCORRM)   Equation (19)

Charge at input terminals 280-1 and 280-2 must be conserved (as notedearlier). Therefore equating equations 18 and 19 and re-arranging theterms gives:C _(s)(INCM−INPCM)+C _(p)INCM+C _(x)(INCM−INCORRP)=C _(s)(AMPCM−OUTCM)+C_(p) APMPCM+C _(x)(AMPCM−INCORRM)   Equation (20)

Rearranging the terms of equation 20 gives:(C _(s) +C _(p) +C _(x))(INCM)−C _(s)(INPCM)−C _(x)(INCORRP)=AMPCM(C_(s) +C _(p) +C _(x))−C _(s)(OUTCM)−C _(x)(INCORRM)   Equation (21)

Therefore, from equation 21 and equation 18A AMPCM is given by$\begin{matrix}\begin{matrix}{{AMPCM} = {{INCM} +}} \\{{C_{s}\frac{\left( {{OUTCM} - {INPCM}} \right)}{C_{s} + C_{p} + C_{x}}} -} \\{2C_{x}\frac{VCORR}{C_{s} + C_{p} + C_{x}}}\end{matrix} & {{Equation}\quad(22)}\end{matrix}$

From equation 22, it may be seen that if the value of (Cs*(OUTCM−INPCM))is made equal to the value of (2*Cx*VCORR), then AMPCM becomes equal toINCM, which is the desired value.

To satisfy the above requirement, the values of Cx and VCORR may bechosen as described below.

A value of Cx may be chosen such that Cx=Cs/G, where G is a large gainvalue. With Cx being made equal to Cs/G, the required value ofcorrection voltage VCORR becomes equal to G/2*(OUTCM−INPCM).

That is: $\begin{matrix}{{{C_{x} = {C_{s}/G}};}{{VCORR} = {\frac{G}{2}\left( {{OUTCM} - {INPCM}} \right)}}} & {{Equation}\quad(23)}\end{matrix}$

The required value of VCORR (as given by equation 23) may be generatedin a manner described with respect to FIG. 4A. INCORRP and INCORRM maybe generated satisfying the relation given by equation 18A by any ofwell known approaches.

Thus, input common-mode range may be improved by generating and applyinga correction voltage. Effect on differential gain can be avoided byapplying equal and opposite voltages appropriately during the sample andhold phases through low-valued capacitors, as described above.

The above described technique uses differential amplifier 420 in thecorrection generation circuitry. Differential amplifier 420 is typicallychosen to be a low speed amplifier in order to minimize powerconsumption. Therefore, the technique described above applies acorrection voltage which is proportional to an average value of commonmode voltage on an input signal.

In environments where the common-mode voltage on an input signal variessignificantly over time periods which are of the same order as thesample and hold phases (of differential amplifier 260), it is desirableto correct for such variations in short durations. For example, in anenvironment where the input is a single ended signal (one terminal ofdifferential amplifier 420 receiving such an input and the otherterminal of differential amplifier 420 tied to a constant voltage), theinput common mode could vary significantly between successive cycles.

The technique described above will require a high power differentialamplifier for generating the correction voltage fast enough to track theinput common mode variations. As such, it is desirable to correct forcommon-mode variations on an input signal on a cycle-by-cycle basis(i.e., at every sample or hold phase) using a different approach. Thisis described below with respect to another aspect of the presentinvention.

5. Providing Cycle-by-Cycle Correction for Input Common-Mode Voltage

FIG. 8A is a circuit diagram of a sample and hold amplifier (SHA)illustrating the manner in which correction voltages can be applied on acycle-by-cycle basis. Sample and hold amplifier SHA 800 (which can beused in place of SHA 110) is shown containing differential amplifier260, switches 250-1, 250-2, 220-1, 220-2, 240-1, 240-2, 801-1, 801-2,801-3, 801-4. 802-1, 802-2, 802-3 and 802-4, and capacitors 210-1,210-2, 230-1, 230-2, 811-1, 811-2, 811-3, 811-4, 812-1, 812-2, 812-3 and812-4. Each component is described below in further detail.

Differential amplifier 260, switches 250-1, 250-2, 220-1, 220-2, 240-1and 240-2, and capacitors 210-1, 210-2, 230-1 and 230-2 operate similarto as described above with respect to FIG. 2, and the description is notrepeated in the interest of conciseness.

Switches 801-1 through 801-4 and 802-1 through 802-4 are used to apply acorrection voltage REFP (present on terminal 840-1) or REFM (present onterminal 840-2) to each of correction capacitors 811-1 through 811-4 and812-1 through 812-4. REFP (840-1) and REFM (840-2) are generatedinternally in differential amplifier 260 in order to maintain thecommon-mode voltage at output terminals 270-1 and 270-2 at a constantlevel equal to (REFP+REFM)/2 (also equal to OUTCM).

The common-mode voltage on an input signal (on terminals 290-1 and290-2) is measured during the sample phase and correction is appliedduring the hold phase.

A measurement circuitry determines the input common-mode voltage andcontains logic which connects switches 801-1 through 801-4 and 802-1through 802-4 to either REFP or REFM.

Five levels of correction voltage may be applied based on the followingswitch connections:

The 5 levels are as follows:

1. All eight of capacitors 801-1 through 801-4 and 802-1 through 802-4connected to REFP.

2. Any three of capacitors 801-1 through 801-4 connected to REFP,remaining one of capacitors 801-1 through 801-4 connected to REFM, anythree of capacitors 802-1 through 802-4 connected to REFP, remaining oneof capacitors 802-1 through 802-4 connected to REFM.

3. Any two of capacitors 801-1 through 801-4 connected to REFP,remaining two of capacitors 801-1 through 801-4 connected to REFM, anytwo of capacitors 802-1 through 802-4 connected to REFP, remaining twoof capacitors 802-1 through 802-4 connected to REFM.

4. Any one of capacitors 801-1 through 801-4 connected to REFP,remaining three of capacitors 801-1 through 801-4 connected to REFM, anyone of capacitors 802-1 through 802-4 connected to REFP, remaining threeof capacitors 802-1 through 802-4 connected to REFM.

5. All eight of capacitors 801-1 through 801-4 and 802-1 through 802-4connected to REFM.

Thus, five levels of correction are applied based on the measured inputcommon-mode voltage.

As mentioned earlier, the addition of these extra capacitors have anundesirable effect on the gain as well as bandwidth of the amplifier. Soit is desirable to make these capacitors smaller. One way to do this isby choosing a high value of REFP and a low value of REFM. This resultsin a reduction in the value of the capacitors for the same range ofcorrection.

The technique of FIG. 8A can be extended to the case when an inputsignal is single ended, and is briefly noted below with respect to FIG.8B.

FIG. 8B shows the circuit of FIG. 8A receiving a single ended signal.Since the internal details of the circuit of FIG. 8B are substantiallythe same as that of FIG. 8A, in the interest of conciseness only thedifferences will be noted below.

As illustrated by arrow 830, a single-ended input signal is appliedacross path (terminal) 290-1 and a ground terminal 820. A constantvoltage is applied on terminal (path) 290-2.

SHA 800 of FIG. 8B works in a manner similar to the description of FIG.8A, and is not repeated here in the interest of conciseness.

The measurement circuitry and switch control logic used in thecorrection procedures described thus far are described next with respectto FIG. 9.

6. Measurement Circuitry and Switch Control Logic

FIG. 9 is a block diagram of a circuit that may be used for measuringthe input common-mode voltage and appropriately connecting correctioncapacitors 811-1 through 811-4 and 812-1 through 812-4 (of FIGS. 8A and8B) to either REFP or REFM. The block diagram is shown containingresistors 905 and 910, flash ADC 920 and switch logic 940.

Resistors 905 and 910 have the same value and are used to form a voltagedivider network to generate a voltage on path 915 which is the average(and therefore equal to the common mode voltage of the input signal) ofthe input voltage present on terminals 905 and 910.

Flash ADC 920 converts the voltage on path 915 and generates anequivalent digital representation which is forwarded to switch logic 940on path 924. Flash ADC 920 is shown as an ADC having 4 threshold levels.This results in a total of 5 different possible corrections based on therange of the input.

Switch logic 940 generates signals 951 through 954 which controlconnection of correction capacitors 811-1 through 811-4 and 812-1through 812-4(of FIGS. 8A and 8B) to either REFP or REFM. Switch logic940 may be implemented using any of several well known approaches.

Flash ADC and switch logic 940 are high speed devices, while theyconsume low power (in comparison with differential amplifier 260 ofFIGS. 4A and 4B). Therefore switches 811-1 through 811-4 and 812-1through 812-4 (of FIGS. 8A and 8B) can be operated at a rate equal tothe sample and hold phases of differential amplifier 260, and correctioncan be applied on a cycle-by-cycle basis while maintaining the powerconsumption of the correction circuitry low.

From the above described sections it may be seen that correction may beapplied either at continuous levels or discrete levels in order tomaintain the input common-mode voltage substantially constant. Examplefigures may be used to illustrate such correction graphically as shownbelow.

7. Graphical Illustration of Correction of Input Common-Mode Voltage

FIGS. 10A and 10B generally illustrate graphically the correction of aninput common-mode voltage. In particular, FIG. 10A illustratescorrection when the correction levels are continuous. Line 1020represents the possible input common-mode voltages selected ascontinuous increasing values, merely for illustration. Lines 1010 and1030 represent the correction voltage applied and the correctedcommon-mode voltage respectively for the corresponding common modevoltage on line 1020.

As may be appreciated, the magnitude of correction voltage (1010) has apositive correlation with the input common mode voltage (1020) so as tomaintain the corrected common mode voltage (1030) substantiallyconstant.

FIG. 10B illustrates correction when the correction levels are discrete.Line 1050 represents the possible input common-mode voltages similar toas in line 1020. Waveforms 1040 and 1060 represent the correctionvoltage applied and the corrected common-mode voltage respectively.Here, the correction is applied as increasing steps and the correctedcommon mode voltage is maintained substantially constant as a result.

SHA 500, SHA 700 and SHA 800 thus designed, can be implemented invarious devices. An example device is described below in further detail.

8. Device

FIG. 11 is a block diagram of receiver system 1100 illustrating anexample system in which various aspects of the present invention may beimplemented. For illustration, it is assumed that receiver system 1100is implemented within a wireless receiver. However, receiver system 1100can be implemented in other devices (wireless as well as wire-basedcommunications) as well.

Receiver system 1100 is shown containing low noise amplifiers (LNA)1110, mixer 1120, filter circuit 1160, analog to digital converter (ADC)1170, and processor 1180. Each block/stage is described in furtherdetail below.

LNA 1110 receives signals on path 1101 and amplifies the receivedsignals to generate a corresponding amplified signal on path 1112. Forexample, in wireless systems, the signals that are transmitted fromsatellites, etc. may be received by an antenna (not shown) and thereceived signals are provided on path 1101. The received signals may beweak in strength and thus amplified by LNA 1110 for further processing.LNA 1110 may be implemented in a known way.

Mixer 1120 may be used to down-convert the received amplified signal onpath 1112 into an intermediate signal with the frequency band ofinterest centered at a lower frequency than the carrier frequency of thereceived signal. In an embodiment, a signal with the frequency band ofinterest centered at 2.4 GHZ (carrier frequency) is converted to asignal with the frequency band of interest centered at zero frequency.

Mixer 1120 may receive the amplified signal on path 1112 and a signal offixed frequency on path 1122 as inputs, and provides the intermediatesignal on path 1126. The signal of fixed frequency on path 1122 may begenerated by a phase locked loop (not shown) in a known way.

Filter circuit 1160 may correspond to a low pass filter, which allowsthe desired low frequencies and rejects all other unwanted highfrequencies present in the signal received on line 1126. The filteredsignal, which contains the frequency band of interest, is provided onpath 1167.

ADC 1170 converts (samples) the filtered signal received on path 1167 toa corresponding digital value, which represents the signal of interestin received signal 1101. Processor 1180 processes the received digitalvalues to provide various user applications and may be implemented asmultiple processing units, each potentially operating independently. ADC1170 may be implemented using various features described in sectionsabove.

9. Conclusion

While various embodiments of the present invention have been describedabove, it should be understood that they have been presented by way ofexample only, and not limitation. Thus, the breadth and scope of thepresent invention should not be limited by any of the above describedexemplary embodiments, but should be defined only in accordance with thefollowing claims and their equivalents.

1. An integrated circuit processing a first input signal and a secondinput signal both in differential form, wherein said first input signalis characterized by a first signal strength according to a first commonmode voltage and wherein said second input signal is characterized by asecond signal strength according to a second common mode voltage,wherein said first common mode voltage is not equal to said secondcommon mode voltage, said integrated circuit comprising: a correctioncircuit generating a first corrected signal from said first input signaland a second corrected signal from said second input signal, said firstcorrected signal and said second corrected signal having said firstsignal strength and said second signal strength respectively, each ofsaid first corrected signal and said second corrected signal having asubstantially equal common mode voltage; and an amplifier amplifyingsaid first corrected signal and then said second corrected signal,whereby said amplifier can be designed to operate with saidsubstantially equal common mode voltage irrespective of the common modevoltage of the input signals to said integrated circuit.
 2. A signalprocessing circuit processing an input signal, said signal processingcircuit comprising: a correction signal generator indicating one of aplurality of correction levels, wherein said plurality of correctionlevels contain more than 2 levels; and a correction circuitry correctinga common mode strength of said input signal to generate a correctedsignal, wherein said correcting is performed based on said one of saidplurality of correction levels, wherein said correcting is performedsuch that said common mode strength of said corrected signal ismaintained at least substantially constant without changing adifferential strength represented by said input signal.
 3. The signalprocessing circuit of claim 2, wherein said plurality of correctionlevels are continuous.
 4. The signal processing circuit of claim 3,wherein said input signal is a differential signal and said correctioncircuitry comprises: a first switch, a second switch, a first capacitorand a second capacitor; wherein a first terminal of each of said firstswitch and said second switch receives said one of said plurality ofcorrection levels during a hold phase, said first terminal of each ofsaid first switch and said second switch receives a first referencevoltage during a sample phase, a second terminal of each of said firstswitch and said second switch is coupled to a first terminal of each ofsaid first capacitor and second capacitor, said corrected signal isprovided in differential form on a second terminal of each of said firstcapacitor and said second capacitor.
 5. The signal processing circuit ofclaim 3, wherein said input signal is a differential signal and saidcorrection circuitry comprises: a first switch, a second switch, a firstcapacitor and a second capacitor; wherein a first terminal of each ofsaid first switch and said second switch receives said one of saidplurality of correction levels during a sample phase, said firstterminal of each of said first switch and said second switch receives asignal of opposite polarity of said one of said plurality of correctionlevels during a hold phase, a second terminal of each of said firstswitch and said second switch is coupled to a first terminal of each ofsaid first capacitor and second capacitor, said corrected signal isprovided in differential form on a second terminal of each of said firstcapacitor and said second capacitor.
 6. The signal processing circuit ofclaim 3, further comprising: a differential amplifier; a third capacitorand a fourth capacitor; a first pair of switches, a second pair ofswitches and a third pair of switches; wherein a first terminal of eachof said first pair of switches receives said input signal, a secondterminal of each of said first pair of switches is coupled to a firstterminal of each of said third capacitor and said fourth capacitor, asecond terminal of each of said third capacitor and fourth capacitor iscoupled to an input inverting terminal and an input non-invertingterminal respectively of said differential amplifier, a first terminalof each of said second pair of switches is coupled to an outputnon-inverting terminal and an output inverting terminal respectively ofsaid differential amplifier, a second terminal of each of said secondpair of switches is coupled to said first terminal of each of said thirdcapacitor and said fourth capacitor, each of said output non-invertingterminal and said output inverting terminal of said differentialamplifier is characterized by a common-mode voltage caused by said firstreference voltage, a first terminal of each of said third pair ofswitches receives a second reference voltage, a second terminal of eachof said third pair of switches is coupled to said input invertingterminal and said input non-inverting terminal respectively of saiddifferential amplifier.
 7. The signal processing circuit of claim 6,wherein said correction signal generator comprises: a first resistor, asecond resistor, and another differential amplifier, wherein a firstterminal of said first resistor and a second terminal of said secondresistor receive said input signal, a second terminal of said firstresistor is coupled to a first terminal of said second resistor, saidsecond terminal of said first resistor is further coupled to one of aninverting terminal and a non-inverting terminal of said anotherdifferential amplifier, another one of said inverting terminal and anon-inverting terminal of said another differential amplifier is coupledto said reference signal, an output terminal of said anotherdifferential amplifier providing said plurality of correction levels. 8.The signal processing circuit of claim 6, wherein said correction signalgenerator comprises: a first resistor, a second resistor, and anotherdifferential amplifier, wherein a first terminal of said first resistorand a second terminal of said second resistor receive said input signal,a second terminal of said first resistor is coupled to a first terminalof said second resistor, said second terminal of said first resistor isfurther coupled to one of an inverting terminal and a non-invertingterminal of said another differential amplifier, another one of saidinverting terminal and a non-inverting terminal of said anotherdifferential amplifier is coupled to said reference signal, two outputterminals of said another differential amplifier providing saidplurality of correction levels in differential form.
 9. The signalprocessing circuit of claim 2, wherein said plurality of correctionlevels are discrete and said input signal is differential.
 10. Thesignal processing circuit of claim 9, wherein said correction circuitrycomprises: a first set of switches, a second set of switches, a firstgroup of capacitors and a second group of capacitors, wherein said firstset of switches, said second set of switches, said first group ofcapacitors and said second group of capacitors are equal in number, afirst terminal of each switch in a first subset of switches receives afirst reference voltage during a hold phase, and a first terminal ofeach switch in a second subset of switches receives a second referencevoltage also during said hold phase, wherein said first subset ofswitches and said second subset of switches are together comprised insaid first set of switches and said second set of switches, and whereinsaid first subset of switches and said second subset of switches aredetermined based on said indicating one of a plurality of correctionlevels, each of said first terminal of each switch in a first subset ofswitches and each of said first terminal of each switch in a secondsubset of switches is connected to a constant common reference voltageduring a sample phase, a second terminal of each switch in said firstset of switches is coupled to a first terminal of a correspondingcapacitor in said first group of capacitors, a second terminal of eachswitch in said second set of switches is coupled to a first terminal ofa corresponding capacitor in said second group of capacitors, and saidcorrected signal is provided in differential form on a second terminalof each capacitor in said first group and said second group ofcapacitors.
 11. The signal processing circuit of claim 9, furthercomprising: a differential amplifier, a first capacitor and a secondcapacitor; a first pair of switches, a second pair of switches and athird pair of switches; wherein a first terminal of each of said firstpair of switches receives said input signal, a second terminal of eachof said first pair of switches is coupled to a first terminal of each ofsaid first capacitor and said second capacitor, a second terminal ofeach of said first capacitor and said second capacitor is coupled tosaid input inverting terminal and said input non-inverting terminalrespectively of said differential amplifier, a first terminal of each ofsaid second pair of switches is coupled to an output non-invertingterminal and an output inverting terminal respectively of saiddifferential amplifier, a second terminal of each of said second pair ofswitches is coupled to said first terminal of each of said firstcapacitor and said second capacitor, each of said output non-invertingterminal and said output inverting terminal of said differentialamplifier is characterized by a common-mode voltage caused by said firstreference voltage and said second reference voltage, a first terminal ofeach of said third pair of switches receives another reference signal,and a second terminal of each of said third pair of switches is coupledto said input inverting terminal and said input non-inverting terminalrespectively of said differential amplifier.
 12. The signal processingcircuit of claim 11, wherein said correction signal generator comprises:a first resistor, a second resistor, a flash ADC and a switch logicblock wherein a first terminal of said first resistor and a secondterminal of said second resistor receive said input signal, a secondterminal of said first resistor is coupled to a first terminal of saidsecond resistor, said second terminal of said first resistor is furthercoupled to an input of said flash ADC, a plurality of outputs of saidflash ADC are coupled to a plurality of inputs of said switch logicblock, and a plurality of outputs of said switch logic block indicatingsaid one of a plurality of correction levels.
 13. The signal processingcircuit of claim 2, wherein said plurality of correction levels arediscrete and said input signal is in single-ended form.
 14. The signalprocessing circuit of claim 13, wherein said correction circuitrycomprises: a first set of switches, a second set of switches, a firstgroup of capacitors and a second group of capacitors, wherein said firstset of switches, said second set of switches, said first group ofcapacitors and said second group of capacitors are equal in number, afirst terminal of each switch in a first subset of switches receives afirst reference voltage during a hold phase, and a first terminal ofeach switch in a second subset of switches receives a second referencevoltage also during said hold phase, wherein said first subset ofswitches and said second subset of switches are together comprised insaid first set of switches and said second set of switches, and whereinsaid first subset of switches and said second subset of switches aredetermined based on said indicating one of a plurality of correctionlevels, each of said first terminal of each switch in a first subset ofswitches and each of said first terminal of each switch in a secondsubset of switches is connected to a constant common reference voltageduring a sample phase, a second terminal of each switch in said firstset of switches is coupled to a first terminal of a correspondingcapacitor in said first group of capacitors, a second terminal of eachswitch in said second set of switches is coupled to a first terminal ofa corresponding capacitor in said second group of capacitors, and saidcorrected signal is provided in differential form on a second terminalof each capacitor in said first group and said second group ofcapacitors.
 15. The signal processing circuit of claim 13, furthercomprising: a differential amplifier; a first capacitor and a secondcapacitor; a first pair of switches, a second pair of switches and athird pair of switches; wherein a first terminal of one of said firstpair of switches receives said input signal, a second terminal of eachof said first pair of switches is coupled to a first terminal of each ofsaid first capacitor and said second capacitor, a second terminal ofeach of said first capacitor and said second capacitor is coupled to aninput inverting terminal and an input non-inverting terminalrespectively of said differential amplifier, a first terminal of each ofsaid second pair of switches is coupled to an output non-invertingterminal and an output inverting terminal respectively of saiddifferential amplifier, a second terminal of each of said second pair ofswitches is coupled to said first terminal of each of said firstcapacitor and said second capacitor, each of said output non-invertingterminal and said output inverting terminal of said differentialamplifier contains said reference voltage, a first terminal of each ofsaid third pair of switches receives another reference signal, and asecond terminal of each of said third pair of switches is coupled tosaid input inverting terminal and said input non-inverting terminalrespectively of said differential amplifier.
 16. The signal processingcircuit of claim 15, wherein said correction signal generator comprises:a first resistor, a second resistor, a flash ADC and a switch logicblock wherein a first terminal of said first resistor and a secondterminal of said second resistor receive said input signal, a secondterminal of said first resistor is coupled to a first terminal of saidsecond resistor, said second terminal of said first resistor is furthercoupled to an input of said flash ADC, a plurality of outputs of saidflash ADC are coupled to a plurality of inputs of said switch logicblock, and a plurality of outputs of said switch logic block indicatingsaid one of a plurality of correction levels.
 17. A device comprising: acorrection signal generator indicating one of a plurality of correctionlevels, wherein said plurality of correction levels contain more than 2levels; a correction circuitry correcting a common mode strength of aninput signal to generate a corrected signal, wherein said correcting isperformed based on said one of said plurality of correction levels,wherein said one of said plurality of correction levels is generatedsuch that a common mode strength of said corrected signal is maintainedat least substantially constant without changing a differential strengthrepresented by said input signal; a processing block processing saidcorrected signal.
 18. The device of claim 17, further comprising ananalog to digital converter (ADC) generating a plurality of digitalvalues from said corrected signal, wherein said processing blockcomprises a processor which processes said plurality of digital values.19. The device of claim 18, wherein said correction circuitry iscomprised in a sample and hold circuitry of said ADC, wherein saidsample and hold circuitry receives said input signal.
 20. The device ofclaim 19, wherein said plurality of correction levels are continuous andsaid input signal is differential.
 21. The device of claim 19, whereinsaid plurality of correction levels are discrete.
 22. The device ofclaim 21, wherein said input signal is differential.
 23. The device ofclaim 21, wherein said input signal is single-ended.
 24. A method ofgenerating a corrected signal from an input signal, each of saidcorrected signal and said input signal being in a differential form,said method comprising: receiving said input signal on a first terminaland a second terminal in said differential form, wherein said inputsignal is characterized by a common mode voltage which can vary bydifferent magnitudes over time, said input signal being alsocharacterized by a corresponding strength equaling a difference oflevels of said input signal on said first terminal and said secondterminal; and processing said input signal to generate said correctedsignal, wherein said processing is performed to correct said common modevoltage with a correction voltage such that said common mode voltage ofsaid corrected signal is maintained to be at least substantiallyconstant without changing said corresponding strength, wherein saidcorrection voltage is at one of a number of levels greater than 2 and isproportionate to said common mode voltage of said input signal.
 25. Themethod of claim 24, wherein said correction voltage is at continuouslevels.
 26. The method of claim 25, wherein said processing comprises:measuring said common mode voltage of said input signal to generate avoltage equal to said common mode voltage of said input signal;generating an amplified voltage equal to an amplified difference of areference voltage and said voltage; and using said amplified differenceto generate said corrected signal.
 27. The method of claim 26, whereinsaid corrected signal in said differential form is provided on ainverting terminal and a non-inverting terminal of a differentialamplifier, said using comprises: applying said amplified voltage througha capacitor to one of said inverting terminal and said non-invertingterminal during a hold phase; applying said amplified voltage throughanother capacitor to the other one of said inverting terminal and saidnon-inverting terminal during said hold phase; and applying saidreference voltage to each of said inverting terminal and saidnon-inverting terminal through said capacitor and said another capacitorduring a sample phase.
 28. The method of claim 26, wherein saidcorrected signal in said differential form is provided on an invertingterminal and a non-inverting terminal of a differential amplifier, saidforming comprises: applying said amplified voltage through a capacitorto one of said inverting terminal and said non-inverting terminal duringa hold phase; applying said amplified voltage through another capacitorto the other one of said inverting terminal and said non-invertingterminal during said hold phase; and applying an opposite polarity ofsaid amplified voltage to each of said inverting terminal and saidnon-inverting terminal through said capacitor and said another capacitorduring a sample phase.
 29. The method of claim 24, wherein saidcorrection voltage is at one of a plurality of discrete levels.
 30. Themethod of claim 29, wherein said processing comprises: measuring saidcommon mode voltage of said input signal to determine one of saidplurality of discrete levels; and forming said correction voltagecorresponding to said one of said plurality of discrete levelsdetermined by said measuring.
 31. The method of claim 30, wherein saidcorrected signal in said differential form is provided on a invertingterminal and a non-inverting terminal of a differential amplifieroperated in a switched capacitor circuit, said forming comprises:applying, during a hold phase of said differential amplifier, one of tworeference voltages to a first set of correction capacitors and the otherof said two reference voltages to a second set of correction capacitors,wherein said first set of correction capacitors and said second set ofcorrection capacitors is determined based on said measuring, andapplying a constant common reference voltage to said first and secondsets of correction capacitors during a sample phase of said differentialamplifier, wherein said first set of correction capacitors and saidsecond set of correction capacitors are together comprised in a firstgroup of capacitors and a second group of capacitors, wherein said firstgroup of capacitors is connected to said inverting terminal and saidsecond group of capacitors is connected to said non-inverting terminal,wherein said first group of capacitors and said second group ofcapacitors are equal in number.
 32. A method of generating a correctedsignal from an input signal, said method comprising: receiving saidinput signal on a terminal of a differential amplifier, wherein theterminals of said differential amplifier are characterized by a commonmode voltage which can vary by different magnitudes over time because ofsaid receiving said input signal; and processing said input signal togenerate said corrected signal, wherein said processing is performed tocorrect said common mode voltage with a correction voltage such thatsaid common mode voltage on said terminals of said differentialamplifier is maintained to be at least substantially constant, whereinsaid correction voltage is at one of a number of levels greater than 2and is proportionate to said common mode voltage of said input signal.33. The method of claim 32, wherein said processing comprises: measuringa strength of said input signal to determine said one of said number oflevels; and forming said correction voltage corresponding to said one ofsaid number of discrete levels determined by said measuring.
 34. Themethod of claim 33, wherein said forming comprises: applying, during ahold phase of said differential amplifier, one of two reference voltagesto a first set of correction capacitors and the other of said tworeference voltages to a second set of correction capacitors, whereinsaid first set and second set of correction capacitors is determinedbased on said measuring, and applying a constant common referencevoltage to said first and second sets of correction capacitors during asample phase of said differential amplifier, wherein said first set ofcorrection capacitors and said second set of correction capacitors aretogether comprised in a first group of capacitors and a second group ofcapacitors, wherein said first group of capacitors is connected to saidinverting terminal and said second group of capacitors is connected tosaid non-inverting terminal, wherein said first group of capacitors andsaid second group of capacitors are equal in number.